When does Gateflow Expand activate?

It activates automatically when your request is complex or has an ambiguity score between 0.70 and 0.85, ensuring the AI fully understands your hardware requirements before coding begins.

Can I skip the clarification questions?

Yes, the skill always provides a 'Quick Start' option that uses sensible defaults to proceed immediately with your task without manual input.

How does this improve RTL code generation?

By capturing specific constraints and architectural choices early, it provides backend agents with the precise context needed to write synthesis-ready and lint-clean SystemVerilog.

Does it support debugging existing code?

Yes, it includes specialized workflows to help identify symptoms like simulation hangs or incorrect outputs before handing the task to a debugging agent.

What kind of hardware questions does it ask?

It focuses on critical hardware details such as interface protocols (AXI, Valid/Ready), testbench requirements, and specific simulation symptoms like X-values.

Gateflow Expand

Name: Gateflow Expand
Author: codejunkie99

bycodejunkie99

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Herramientas para Desarrolladores

Refines ambiguous hardware design requests through interactive clarification and expert architectural options.

Gateflow Expand acts as an intelligent triage and planning layer for SystemVerilog development within the Gateflow ecosystem. It activates when user intent is complex or ambiguous, guiding developers through targeted questions regarding interface protocols, debug symptoms, or architectural depth. By presenting structured implementation options with detailed pros and cons, it ensures that Claude has the precise context needed to generate high-quality RTL code or simulation testbenches, significantly reducing iterative errors and streamlining the handoff to specialized Gateflow agents.

Características Principales

01Intelligent intent disambiguation with confidence-based activation

02Quick Start defaults for rapid prototyping and exploration

03Enriched JSON context generation for seamless subagent handoffs

04Architectural trade-off analysis for protocols like AXI-Stream and AXI-Lite

05Context-aware question templates for RTL creation, debugging, and planning

0635 GitHub stars

Casos de Uso

01Selecting the optimal hardware interface protocol based on project constraints

02Diagnosing complex simulation failures through symptom-based triaging

03Narrowing down technical specifications for new SystemVerilog modules

What are Skills?·How to Install

Install with 🐟 Skill.Fish

npx skillfish add codejunkie99/gateflow-plugin gf-expand

For use in Claude.ai and ChatGPT

Download Skill