What naming conventions does this SystemVerilog skill follow?

It enforces the 'svc_' prefix for modules, 'clk' for clocks, 'rst_n' for active-low resets, and specific suffixes for pipeline stages (_p1, _p2) and next-cycle signals (_next).

What is the recommended structure for a SystemVerilog module?

The skill organizes modules in a specific order: localparams, internal signals, child module instantiations, combinational logic (always_comb), sequential logic (always_ff), and finally formal assertions.

How does the skill handle synchronous resets?

The skill mandates a synchronous active-low reset pattern within always_ff blocks, ensuring that all registers are properly initialized on the rising edge of the clock when rst_n is low.

Does this skill help with code formatting and linting?

Yes, it provides specific alignment rules for signal declarations and instructs the user to run 'make format' and 'make lint' after writing code to ensure compliance.

SystemVerilog Writing Standards

Name: SystemVerilog Writing Standards
Author: pbozeman

bypbozeman

Herramientas para Desarrolladores

Enforces standardized SystemVerilog coding conventions, reset patterns, and module structures for high-quality hardware design.

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The Writing SystemVerilog skill equips Claude with the specific expertise needed to author high-quality RTL code within the SVC ecosystem. It automates the application of naming conventions, structures modules in a logical order (from localparams to assertions), and enforces specific styles for comments and signal declarations. This skill is particularly useful for hardware engineers looking to maintain consistency across large FPGA or ASIC projects, ensuring that state machines, resets, and signal logic follow industry best practices for synthesizability and readability.

Características Principales

0 GitHub stars
Implements consistent synchronous active-low reset patterns
Standardizes module organization from signal declarations to formal assertions
Provides templates for robust FSM design using typedef enums and logic separation
Enforces 'svc_' naming prefixes and specific signal suffixes like '_next' and '_p1'
Guides the use of the SVC_UNUSED macro and integrated linting workflows

Casos de Uso

Implementing complex finite state machines with clear separation of transition and output logic
Developing new SystemVerilog modules from scratch with correct boilerplate and structure
Refactoring legacy RTL code to meet modern coding and naming standards

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Características Principales

0 GitHub stars
Implements consistent synchronous active-low reset patterns
Standardizes module organization from signal declarations to formal assertions
Provides templates for robust FSM design using typedef enums and logic separation
Enforces 'svc_' naming prefixes and specific signal suffixes like '_next' and '_p1'
Guides the use of the SVC_UNUSED macro and integrated linting workflows

Casos de Uso

Implementing complex finite state machines with clear separation of transition and output logic
Developing new SystemVerilog modules from scratch with correct boilerplate and structure
Refactoring legacy RTL code to meet modern coding and naming standards