Circuit Fibonacci & Square Root Implementation

概要

This skill provides specialized guidance for architecting mathematical computations—such as integer square roots and Fibonacci sequences—using low-level gate netlists. It emphasizes a robust, component-first development workflow that includes hardware-centric paper-tracing, gate count estimation to meet resource constraints, and the modular construction of arithmetic building blocks like ripple-carry adders and comparators. By following established best practices for event-driven simulation and feedback loops, it enables the creation of efficient, debuggable circuits within text-based simulation environments.

主な機能

• Strategies for implementing multi-bit arithmetic operations like adders and comparators
• Component-first development methodology for gate-level logic
• 16 GitHub stars
• Comprehensive verification and unit testing strategies for hardware logic components
• Guidance for managing feedback loops and sequential state machines in event-driven simulators
• Resource estimation techniques to minimize gate counts and optimize hardware efficiency

ユースケース

• Designing mathematical function circuits for text-based gate simulators
• Debugging complex logic circuits involving feedback loops and iterative calculations
• Optimizing gate-level implementations to fit within strict hardware resource limits