What types of hardware issues can it detect?

It identifies critical RTL design flaws such as unused signals, width mismatches, case statement incompleteness, and unintended latch inference.

Do I need to provide file paths every time?

No, the skill can automatically detect SystemVerilog files (.sv) in your current directory and RTL subfolders if no specific files are provided.

Is this skill specific to a particular FPGA vendor?

No, it uses Verilator which is vendor-neutral and follows IEEE 1800 SystemVerilog standards, making it compatible with any hardware design flow.

What tool does Gateflow Lint use for analysis?

It utilizes Verilator, a high-performance open-source SystemVerilog simulator and linting tool, to perform static analysis on your RTL files.

Can it fix the errors it finds automatically?

While the lint skill itself identifies and explains errors, it is designed to work with the Gateflow orchestrator to trigger refactoring agents that can suggest or apply fixes.

Gateflow SystemVerilog Lint

Name: Gateflow SystemVerilog Lint
Author: codejunkie99

bycodejunkie99

•

セキュリティとテスト

Lints SystemVerilog code using Verilator to identify design errors, warnings, and performance bottlenecks with structured feedback.

Gateflow Lint is a specialized static analysis tool designed for hardware engineers using Claude Code. It leverages Verilator to perform comprehensive checks on SystemVerilog RTL, categorizing issues into errors and warnings while providing human-readable explanations for common design pitfalls. By generating a machine-parseable result block, it allows the Gateflow orchestrator to automatically trigger refactoring steps, making it an essential component for high-velocity hardware development and verification.

主な機能

01Machine-parseable output for automated agent orchestration

02Automated Verilator linting for SystemVerilog files

0328 GitHub stars

04Detailed troubleshooting guides for common linting issues

05Automatic detection of local .sv and RTL source files

06Intelligent categorization of RTL errors and warnings

ユースケース

01Verifying RTL design integrity before synthesis or simulation

02Automating hardware debugging workflows within Claude Code

03Explaining complex Verilator warnings to hardware developers

What are Skills?·How to Install

Install with 🐟 Skill.Fish

npx skillfish add codejunkie99/gateflow-plugin gf-lint

For use in Claude.ai and ChatGPT

Download Skill