Architects comprehensive RTL implementation plans and hardware specifications using natural language.
GF Plan is a specialized Claude Code skill designed for hardware engineers to bridge the gap between abstract requirements and SystemVerilog implementation. It enforces a rigorous architectural planning phase, ensuring that critical hardware concepts like clock domains, reset strategies, bus protocols, and FSM logic are defined before a single line of RTL is written. By generating structured Markdown plans and Mermaid diagrams, it provides a clear roadmap for development and a standardized handoff format for coding agents.
主な機能
01Produces structured implementation roadmaps for automated RTL generation
02Integrates with existing codebases to map dependencies and integration points
0335 GitHub stars
04Plans multi-clock domain crossings and reset synchronization strategies
05Generates interactive Mermaid block diagrams and FSM state diagrams
06Defines detailed interface specifications for AXI, APB, and custom protocols
ユースケース
01Architecting complex subsystems like DMA controllers or memory managers
02Creating formal documentation and state machine specifications for hardware reviews
03Planning the integration of new features into existing legacy RTL codebases
