What is the spec_optimizer skill?

The spec_optimizer skill is a specialized capability for Claude Code that enforces a standardized structure for Integrated Circuit (IC) module specifications, covering everything from versioning to verification.

Does it help with the hardware verification process?

Yes, it provides a structured methodology for verification planning, including the definition of stimulus generation strategies, golden model approaches, and test report metrics.

How does it improve hardware documentation?

It ensures that all module specifications include critical sections like semantic versioning, semantically grouped IO signal tables, and a detailed verification plan with test cases.

What is the signal ordering guideline in this skill?

The skill promotes grouping signals by semantic meaning (such as grouping data, valid, and ready signals together) rather than simply grouping by signal direction.

IC Specification Optimizer

Name: IC Specification Optimizer
Author: Devil-SX

byDevil-SX

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学習とドキュメンテーション

Standardizes hardware module specifications by enforcing consistent versioning, interface definitions, and verification methodologies.

概要

The IC Specification Optimizer skill provides a rigorous framework for documenting Integrated Circuit (IC) modules, ensuring that hardware designs are clearly defined before implementation. It mandates semantic versioning, semantically grouped IO tables, and comprehensive verification plans including golden models and test case dependencies. By automating the structure of these technical documents, it helps engineering teams maintain high-quality design standards, reduce ambiguity in signal handoffs, and streamline the transition from architectural specification to RTL coding.

主な機能

Standardizes verification plans including golden model strategies and test case mapping
Enforces semantic versioning (MAJOR.MINOR.PATCH) for hardware modules
Requires semantically grouped IO tables for better architectural clarity
2 GitHub stars
Supports optional FSM descriptions, timing diagrams, and functional pseudocode
Provides templates for test case dependencies and expected output metrics

ユースケース

Creating comprehensive verification plans for IC modules before RTL development
Maintaining consistent technical documentation across hardware engineering repositories
Defining interface signals for complex hardware modules to ensure integration compatibility

概要

主な機能

Standardizes verification plans including golden model strategies and test case mapping
Enforces semantic versioning (MAJOR.MINOR.PATCH) for hardware modules
Requires semantically grouped IO tables for better architectural clarity
2 GitHub stars
Supports optional FSM descriptions, timing diagrams, and functional pseudocode
Provides templates for test case dependencies and expected output metrics

ユースケース

Creating comprehensive verification plans for IC modules before RTL development
Maintaining consistent technical documentation across hardware engineering repositories
Defining interface signals for complex hardware modules to ensure integration compatibility