Does it handle specific hardware interfaces?

Yes, it provides specific guidance for organizing files into subdirectories such as AXI, CDC, FIFO, and UART based on the module's primary function.

Can I use this for non-SVC projects?

While it is optimized for the SVC repository structure, the SystemVerilog patterns and best practices it implements are widely applicable to most professional hardware projects.

How does this skill help with code quality?

It includes an integrated checklist that reminds developers to use uppercase include guards, align port declarations, and run linting/formatting tools before committing.

What is the primary purpose of the SystemVerilog Module Scaffolder?

It generates a standardized template for new SystemVerilog modules, ensuring consistent structure, naming conventions, and port organization for hardware design.

Does the template include boilerplate for logic blocks?

Yes, it includes predefined sections for local parameters, internal signals, combinational logic (always_comb), and sequential logic (always_ff).

SystemVerilog Module Scaffolder

Name: SystemVerilog Module Scaffolder
Author: pbozeman

bypbozeman

開発者ツール

Generates standardized SystemVerilog module templates with built-in include guards, port ordering, and best-practice checklists.

概要

The SystemVerilog Module Scaffolder skill automates the creation of high-quality RTL modules by providing a robust template that adheres to the SVC (SystemVerilog Components) architectural standards. It ensures consistency across hardware designs by automatically handling boilerplate tasks such as include guards, standard port declarations (clock and reset), and logic separation. This skill is particularly useful for hardware engineers who need to maintain clean, lint-ready codebases while accelerating the initial design phase of FPGA or ASIC components.

主な機能

Standardized SystemVerilog template with automated include guards
Directory structure guidance for AXI, CDC, FIFO, and RISC-V modules
Pre-configured port ordering for clk, rst_n, and data signals
Built-in logic blocks for combinational and sequential processes
0 GitHub stars
Integrated quality checklist for formatting and linting compliance

ユースケース

Enforcing consistent coding standards across a team's SystemVerilog repository
Bootstrapping new RTL modules for FPGA or ASIC hardware projects
Rapidly setting up specialized modules like FIFOs, UARTs, or Clock Domain Crossings

概要

主な機能

Standardized SystemVerilog template with automated include guards
Directory structure guidance for AXI, CDC, FIFO, and RISC-V modules
Pre-configured port ordering for clk, rst_n, and data signals
Built-in logic blocks for combinational and sequential processes
0 GitHub stars
Integrated quality checklist for formatting and linting compliance

ユースケース

Enforcing consistent coding standards across a team's SystemVerilog repository
Bootstrapping new RTL modules for FPGA or ASIC hardware projects
Rapidly setting up specialized modules like FIFOs, UARTs, or Clock Domain Crossings