소개
Provides a Model Context Protocol (MCP) server enabling AI assistants like Claude Desktop and Cursor IDE to interact with various open-source EDA tools. It facilitates tasks such as Verilog synthesis using Yosys, Verilog simulation via Icarus Verilog, waveform analysis with GTKWave, and complete RTL-to-GDSII ASIC design flows using OpenLane. The server acts as a unified interface, streamlining hardware design workflows through natural language interaction, making it easier to analyze reports and view layouts for designs.
주요 기능
- Waveform Viewing using GTKWave for VCD file visualization
- ASIC Design Flow automation with OpenLane and Docker integration
- Verilog Synthesis using Yosys for FPGA targets
- Verilog Simulation with Icarus Verilog and automated testbench execution
- 3 GitHub stars
- Layout Viewing in KLayout for physical design inspection
사용 사례
- Synthesizing Verilog code for various FPGA targets using AI assistants
- Simulating hardware designs and analyzing waveforms using natural language commands
- Automating complete RTL-to-GDSII ASIC design flows through AI-driven interaction
Sponsored