Naja Scope

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Explore, navigate, and trace elaborated SystemVerilog, Verilog, and VHDL hardware designs using AI assistants without dumping source RTL into the context.

Naja Scope is a specialized Model Context Protocol (MCP) server built on the najaeda netlist engine that provides AI assistants with structured, token-bounded views of hardware designs. Instead of overloading context windows with massive RTL code dumps, it enables agents like Claude and ChatGPT to ask targeted architectural questions about signal drivers, module hierarchies, logic cones, and exact source references. The server supports both RTL and gate-level netlists with standard-cell Liberty libraries, while preserving design intent such as FSM states and struct fields across SystemVerilog and VHDL designs.

주요 기능

01Combinational fan-in and fan-out logic cone tracing up to register boundaries
02Exact source code navigation linking elaborated design objects back to file:line ranges
03Design intent recovery for enum state names, struct/union fields, and parameter formulas
0422 GitHub stars
05Cross-hierarchy signal driver and load tracing across module boundaries
06Comprehensive support for elaborated SystemVerilog, VHDL (beta), and post-synthesis gate-level netlists

사용 사례

01Assisting hardware engineers in debugging complex signal connectivity and root causes across deep RTL hierarchies
02Inspecting post-synthesis structural netlists alongside Liberty standard-cell libraries to analyze cell distributions and fan-out
03Conducting AI-driven architectural code reviews and register boundary analysis without exceeding context token budgets