Converts TL-Verilog files into SystemVerilog/Verilog by wrapping Redwood EDA’s SandPiper-SaaS compile function.
소개
This MCP server wraps Redwood EDA’s SandPiper-SaaS compile function, enabling the conversion of TL-Verilog (TLV) files into SystemVerilog/Verilog. It exposes every SandPiper flag as its own MCP tool parameter, allowing for detailed introspection and easy automation of the compilation process. Users can specify compiler behavior using natural language, making it highly accessible.
주요 기능
Uses UV for environment and dependency management
Exposes Sandpiper flags as MCP tool parameters
0 GitHub stars
Configurable with Cline/Claude Desktop via JSON
Can be run with UV or UVX
Supports TL-Verilog to SystemVerilog/Verilog conversion
사용 사례
Automating TL-Verilog compilation workflows
Integrating TL-Verilog compilation into MCP-based development environments
Experimenting with different Sandpiper compiler flags
