What is the purpose of the .autochip directory?

It serves as the centralized configuration hub for IC projects, storing environment settings in env.yaml and module metadata in the modules/ directory.

How does the schema validation benefit my workflow?

It ensures that all module JSON files are correctly formatted before processing, preventing errors in automated design or verification pipelines.

Does it support nested submodule hierarchies?

Yes, the skill includes scripts that use recursive $ref resolution to handle and visualize complex, multi-level module dependencies.

Can I use this for Verilog and SystemVerilog projects?

Absolutely. The module definitions are specifically designed to track RTL filepaths, testbenches, golden models, and documentation for hardware designs.

AutoChip IC Design Architect

Name: AutoChip IC Design Architect
Author: Devil-SX

byDevil-SX

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Developer Tools

Manages IC module metadata and project configurations for automated hardware design and verification workflows.

About

The AutoChip Project Architect skill streamlines the management of Integrated Circuit (IC) design projects by providing a standardized configuration structure within the .autochip directory. It enables Claude to interact with hardware module metadata, validate configurations against strict JSON schemas, and resolve complex submodule hierarchies using recursive $ref support. By automating the extraction of module details, RTL paths, and test cases, this skill ensures consistency across hardware descriptions, documentation, and verification environments, making it an essential utility for hardware engineers using AI-assisted design tools.

Key Features

Multi-format reporting including Table, JSON, and Tree views
JSON schema validation for IC module metadata
Automated extraction of test cases and module hierarchies
2 GitHub stars
Standardized .autochip project structure enforcement
Recursive submodule resolution with $ref support

Use Cases

Visualizing complex chip architectures and hierarchical submodule dependencies
Consolidating verification test cases from across multi-module RTL projects
Validating hardware module configurations against predefined IC design schemas

About

Key Features

Multi-format reporting including Table, JSON, and Tree views
JSON schema validation for IC module metadata
Automated extraction of test cases and module hierarchies
2 GitHub stars
Standardized .autochip project structure enforcement
Recursive submodule resolution with $ref support

Use Cases

Visualizing complex chip architectures and hierarchical submodule dependencies
Consolidating verification test cases from across multi-module RTL projects
Validating hardware module configurations against predefined IC design schemas