What makes this different from standard software SemVer?

It adapts versioning criteria specifically for hardware events, such as defining MAJOR increments for IO port changes and PATCH increments for timing violation fixes.

Should the testbench and RTL have different version numbers?

No, this skill promotes a module-independent approach where the version number is shared between both the RTL and its corresponding testbench.

When should I increment the MAJOR version for a chip module?

Increment the MAJOR version when making incompatible changes like adding/removing IO ports, modifying protocols, or making architectural changes that break dependent modules.

Does this skill help with documentation updates?

Yes, documentation updates that do not affect the logic or interface are categorized as PATCH increments under this scheme.

Can this be used for automated hardware release scripts?

Absolutely. It provides the logic needed to automate tagging and versioning within hardware CI/CD pipelines and design management tools.

Chip Semantic Versioning

Name: Chip Semantic Versioning
Author: Devil-SX

byDevil-SX

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Developer Tools

Standardizes hardware versioning by applying MAJOR.MINOR.PATCH conventions specifically to IC modules and RTL design.

About

This skill provides a structured framework for hardware engineers to implement semantic versioning tailored for Integrated Circuit (IC) development and RTL design. It adapts the standard SemVer format to hardware-specific nuances, ensuring that version increments accurately reflect changes in module IO ports, protocol compatibility, and logic fixes. By synchronizing versioning between RTL source code and testbenches, the skill facilitates better coordination in complex hardware projects and improves the traceability of module-independent development cycles.

Key Features

Categorizes logic bug fixes and timing violation corrections as PATCH updates
Specifies MINOR increments for backward-compatible features and test methodology updates
2 GitHub stars
Synchronizes version numbers across both RTL and verification testbench components
Defines MAJOR increments for breaking IO, protocol, or architectural changes
Provides standardized versioning examples for consistent hardware release cycles

Use Cases

Coordinating updates between hardware design and verification teams
Maintaining version consistency across modular IC design releases
Automating the tracking of architectural changes in complex SoC projects

About

Key Features

Categorizes logic bug fixes and timing violation corrections as PATCH updates
Specifies MINOR increments for backward-compatible features and test methodology updates
2 GitHub stars
Synchronizes version numbers across both RTL and verification testbench components
Defines MAJOR increments for breaking IO, protocol, or architectural changes
Provides standardized versioning examples for consistent hardware release cycles

Use Cases

Coordinating updates between hardware design and verification teams
Maintaining version consistency across modular IC design releases
Automating the tracking of architectural changes in complex SoC projects