Orchestrates SystemVerilog development workflows by semantically classifying user intent and routing requests to specialized GateFlow agents.
GF Router serves as the central intelligence and orchestration layer for the GateFlow ecosystem, designed specifically for AI-powered SystemVerilog development. Instead of relying on simple keyword matching, it employs semantic analysis to determine whether a user needs RTL generation, debugging, architectural mapping, or verification. When faced with ambiguous requests, the skill activates an 'Expand Mode' to ask clarifying questions, ensuring that downstream agents receive high-fidelity context, constraints, and file references needed to deliver production-grade hardware designs.
Key Features
01Context Building: Packages original queries, user preferences, and file paths into a structured schema for sub-tasks.
02Dynamic Expand Mode: Triggers interactive clarification when confidence scores are between 0.70 and 0.85.
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04Automated Agent Handoff: Seamlessly transitions tasks to specialized sub-agents like sv-codegen or sv-debug.
05Result Status Handling: Manages completion, errors, and multi-step orchestration chains for complex hardware tasks.
06Semantic Intent Classification: Analyzes user goals to distinguish between RTL creation, debugging, and verification.
Use Cases
01Orchestrating end-to-end development by routing to RTL creation and then automatically triggering testbench generation.
02Identifying when a user is providing a bug report versus asking for general architectural guidance.
03Converting vague requests like 'help with my FIFO' into specific debugging or refactoring tasks through interactive clarification.