What hardware protocols does Gateflow understand?

Gateflow can handle common protocols like AXI, Wishbone, and custom interfaces, using web-fetch tools to verify protocol specifications during the planning phase.

How does Gateflow ensure design quality?

It follows a strict 'Plan First' rule using sv-planner and a mandatory verification gate that requires all code to pass linting and simulation before the task is considered complete.

Can I use Gateflow on existing SystemVerilog projects?

Absolutely. Gateflow can be used to debug existing code, fix lint errors, or implement new features into an established RTL codebase.

What is the Gateflow (gf) skill?

Gateflow is an AI-powered assistant for SystemVerilog development that orchestrates the entire design process, including architecture planning, RTL coding, and verification.

Does Gateflow support simulation and verification?

Yes, Gateflow includes specialized routines for running simulations (gf-sim) and linting (gf-lint), parsing the results to automatically fix bugs or violations.

Gateflow SystemVerilog Orchestrator

Name: Gateflow SystemVerilog Orchestrator
Author: codejunkie99

bycodejunkie99

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Developer Tools

Automates the entire SystemVerilog hardware design lifecycle, from architecture planning and RTL generation to automated linting and simulation-based verification.

Gateflow (gf) is a comprehensive orchestration skill for Claude Code designed to handle end-to-end SystemVerilog development. It coordinates a suite of specialized sub-agents to plan hardware architectures, generate production-grade RTL, run linting checks, and perform simulation-based verification. By enforcing a strict 'plan-first' and 'verify-always' workflow, Gateflow ensures that delivered hardware designs are not just syntactically correct but are functionally verified, lint-clean, and ready for implementation. It is an essential tool for digital logic designers looking to accelerate their RTL development workflow using natural language.

Key Features

01Intelligent iterative debugging for fixing simulation failures and lint errors

02Automated linting and simulation with structured feedback parsing

0328 GitHub stars

04End-to-end RTL orchestration from natural language requirements

05Specialized multi-agent system for planning, coding, and debugging

06Protocol-aware architecture planning with ASCII block diagrams

Use Cases

01Automating the verification and debugging of existing SystemVerilog codebases to ensure lint-clean status

02Rapidly prototyping hardware architectures and testbenches using natural language specifications

03Creating parameterized RTL modules such as FIFOs, UARTs, or complex AXI interconnects

What are Skills?·How to Install

Install with 🐟 Skill.Fish

npx skillfish add codejunkie99/gateflow-plugin gf

For use in Claude.ai and ChatGPT

Download Skill