Which hardware protocols does GF Plan support?

It supports standard industry protocols including AXI4, AXI-Lite, AXI-Stream, APB, AHB, Wishbone, and custom valid/ready handshakes.

Why should I use a planner instead of just asking for code?

Hardware design requires thinking in parallel blocks and strict timing; planning prevents architectural errors that are much harder to fix once the implementation code is written.

What is the primary purpose of GF Plan?

GF Plan is designed to help hardware engineers architect and document RTL designs before writing code, ensuring all interfaces, timing, and logic blocks are correctly specified.

Does this skill generate actual SystemVerilog code?

No, GF Plan focuses on the architectural planning phase. Once a plan is finalized, it is typically handed off to the Gateflow execution tool (/gf) to generate the actual RTL.

Can it handle multi-clock domain designs?

Yes, GF Plan includes specific phases for planning clock domains, resets, and clock domain crossing (CDC) strategies using synchronizers or async FIFOs.

GF Plan - Hardware Design Architect

Name: GF Plan - Hardware Design Architect
Author: codejunkie99

bycodejunkie99

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Developer Tools

Generates comprehensive RTL implementation plans and architectural specifications for SystemVerilog hardware design.

GF Plan is a specialized hardware engineering skill within the Gateflow plugin that structures the design process for complex RTL subsystems. It moves beyond simple code generation by enforcing a rigorous architectural workflow that includes block diagramming, interface specification, and timing analysis. By guiding users through requirement gathering for bus protocols like AXI or APB and defining state machine transitions via Mermaid diagrams, it ensures that hardware designs are logically sound, timing-aware, and ready for high-quality implementation.

Key Features

01Interactive requirement gathering for bus protocols and timing constraints

02Generation of Mermaid-based block diagrams and FSM state charts

03Automated architectural mapping of existing SystemVerilog codebases

0428 GitHub stars

05Detailed interface and port specification with register map planning

06Comprehensive clock domain crossing (CDC) and reset strategy documentation

Use Cases

01Architecting new hardware modules like DMA controllers or UARTs from scratch

02Planning the integration of complex features into existing RTL subsystems

03Generating professional design documentation and implementation roadmaps for handoff

What are Skills?·How to Install

Install with 🐟 Skill.Fish

npx skillfish add codejunkie99/gateflow-plugin gf-plan

For use in Claude.ai and ChatGPT

Download Skill