How does it handle multiple top-level modules?

If multiple potential top modules are detected, GF Sim allows for specifying the target top-module to ensure the correct testbench is executed.

Does it support waveform generation?

Yes, the skill automatically includes the --trace flag during compilation, which enables the generation of VCD files for viewing signal transitions.

What simulator does GF Sim use?

GF Sim utilizes Verilator, an open-source, high-performance SystemVerilog simulator, to convert hardware descriptions into executable binaries for simulation.

Can it distinguish between RTL and Testbench files?

Yes, it uses internal heuristics to identify markers like 'initial' blocks and system tasks for testbenches, versus 'always_ff' or 'always_comb' for synthesizable RTL.

What happens when a simulation fails?

The skill returns a 'FAIL' status in a structured block, which allows orchestration agents to automatically trigger debugging workflows to find the root cause.

GF Sim (SystemVerilog Simulator)

Name: GF Sim (SystemVerilog Simulator)
Author: codejunkie99

bycodejunkie99

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Security & Testing

Compiles and executes SystemVerilog simulations using Verilator with automated file classification and structured result reporting.

GF Sim is a specialized capability for hardware engineers that automates the RTL verification cycle within Claude. It intelligently scans project directories to distinguish between Design Under Test (DUT) and testbench files, orchestrates the Verilator compilation process, and executes simulations to detect functional errors. By generating standardized result blocks and supporting waveform tracing, it allows Claude to act as a high-powered verification assistant that can identify, run, and interpret hardware simulation outcomes with minimal manual configuration.

Key Features

01Real-time simulation log parsing for PASS/FAIL/ERROR status detection

02Automatic VCD waveform generation for post-simulation debugging

03High-performance Verilator integration for fast SystemVerilog compilation

0428 GitHub stars

05Standardized output formatting for seamless integration with /gf orchestration tools

06Automated DUT vs. Testbench file classification using heuristic syntax analysis

Use Cases

01Verifying RTL module functionality immediately after writing or modifying hardware logic

02Running automated regression tests to ensure code changes don't break existing designs

03Identifying and summarizing compilation errors in complex multi-file SystemVerilog projects

What are Skills?·How to Install

Install with 🐟 Skill.Fish

npx skillfish add codejunkie99/gateflow-plugin gf-sim

For use in Claude.ai and ChatGPT

Download Skill