HPCA Experiment Auditor
Audits computer architecture evaluations against rigorous HPCA methodology standards for fidelity, baseline tuning, and workload reporting.
HPCA Experiment Auditor helps computer architecture researchers stress-test their paper evaluations prior to conference submission gates like HPCA, ISCA, and MICRO. It validates the complete fidelity contract (simulator versions, cache hierarchies, timing models, and SimPoint sampling), verifies that claims match their underlying instruments, ensures real-silicon machine states are captured with proper dispersion, and checks that baselines are tuned honestly with per-workload distribution breakdowns.
Key Features
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02Claim-to-instrument credibility mapping across cycle timing, power, silicon, and area
03Baseline tuning verification with parameter sweep validation and loss-case reporting
04Silicon provenance tracking including frequency governors, turbo, SMT, and NUMA policies
05Comprehensive pre-submission checklist generating structured methodology risk assessments
06Fidelity contract auditing for simulators, hardware configurations, and workload sampling
Use Cases
01Identifying unpinned hardware runs, missing error bars, or undertuned baselines before peer review
02Verifying that cycle-level simulation, power models, and silicon measurements appropriately back all paper claims
03Auditing computer architecture experimental setups prior to HPCA, ISCA, or MICRO submission deadlines