MICRO Paper Experiment Design
Guides the design, benchmarking, and rigorous auditing of experimental evaluations for microarchitecture research papers.
MICRO Paper Experiment Design provides microarchitecture researchers with standard evaluation frameworks required by premier venues like IEEE/ACM MICRO. It audits simulation instruments (analytical models, cycle-level simulators like gem5 and ChampSim, RTL, and silicon), verifies robust baseline configurations, enforces rigorous workload sampling (SimPoint, SPEC CPU2017), guides ablation and sensitivity sweeps, and ensures transparent overhead accounting for storage, area, latency, and power.
Key Features
01Aligns empirical claims with appropriate modeling tools on the microarchitecture instrument ladder
02Structures systematic component ablations, parameter sensitivity sweeps, and adversarial test cases
03Audits baseline core configurations, prior state-of-the-art reimplementations, and iso-storage controls
04Generates comprehensive overhead accounting checklists across storage, power, area, and latency
05Enforces rigorous workload sampling, SimPoint reporting, and geometric mean speedup statistics
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Use Cases
01Auditing draft microarchitecture paper evaluations against IEEE/ACM MICRO reviewer expectations
02Structuring ablation studies and sensitivity sweeps to justify hardware mechanism design trade-offs
03Designing cycle-level simulation methodology, baseline configurations, and workload suites for architecture submissions