How does the skill distinguish between DUT and testbench files?

It uses heuristics and grep-based markers, identifying testbenches via keywords like '$display' or 'initial' and identifying DUTs via synthesizable constructs like 'always_ff'.

Can I view waveforms using this skill?

Yes, the skill includes the '--trace' flag during compilation to enable VCD waveform generation for detailed signal analysis.

What happens if there are multiple top-level modules?

If multiple top modules are detected, the skill is designed to use the '--top-module' flag to specify the correct entry point for the simulation.

Which simulator does gf-sim use for SystemVerilog?

The gf-sim skill uses Verilator to compile SystemVerilog code into high-performance executable binaries for simulation.

What is the GATEFLOW-RESULT block?

It is a standardized, machine-readable output block that summarizes the simulation status (PASS/FAIL/ERROR), error counts, and file lists for further automation.

SystemVerilog Simulation Assistant

Name: SystemVerilog Simulation Assistant
Author: codejunkie99

bycodejunkie99

•

Security & Testing

Automates the compilation, execution, and verification of SystemVerilog designs using Verilator with structured status reporting.

The gf-sim skill transforms Claude into a specialized hardware verification tool by managing the full SystemVerilog simulation lifecycle. It intelligently classifies files into Design Under Test (DUT) and Testbench categories, orchestrates the Verilator build process with appropriate flags, and executes simulations to provide parseable pass/fail results. This skill is essential for RTL engineers looking to validate hardware logic, generate waveforms, and automate regression testing directly within their AI-powered development workflow.

Key Features

01Comprehensive error parsing and common issue resolution

02Structured result reporting for automated orchestration

0335 GitHub stars

04Automated DUT and Testbench file classification

05VCD waveform trace generation for debugging

06Verilator-based binary compilation and execution

Use Cases

01Verifying RTL module functionality immediately after design changes

02Streamlining the hardware debugging process with structured status output

03Automated verification of hardware designs against testbench assertions

What are Skills?·How to Install

Install with 🐟 Skill.Fish

npx skillfish add codejunkie99/gateflow-plugin gf-sim

For use in Claude.ai and ChatGPT

Key Features

01Comprehensive error parsing and common issue resolution

02Structured result reporting for automated orchestration

0335 GitHub stars

04Automated DUT and Testbench file classification

05VCD waveform trace generation for debugging

06Verilator-based binary compilation and execution

Use Cases

01Verifying RTL module functionality immediately after design changes

02Streamlining the hardware debugging process with structured status output

03Automated verification of hardware designs against testbench assertions

What are Skills?·How to Install

Install with 🐟 Skill.Fish

npx skillfish add codejunkie99/gateflow-plugin gf-sim

For use in Claude.ai and ChatGPT