关于
MCP4EDA is an advanced Model Context Protocol (MCP) server designed to bridge the gap between AI assistants, such as Claude Desktop and Cursor IDE, and complex Electronic Design Automation (EDA) toolchains. It empowers AI to seamlessly orchestrate and execute hardware design tasks, from initial RTL synthesis and simulation to full RTL-to-GDSII ASIC design flows and detailed waveform analysis, all through a unified and natural language interface. This integration streamlines the entire chip design process, making sophisticated EDA capabilities accessible and automatable via AI.
主要功能
- Layout Viewing of GDSII files and analysis of OpenLane reports with KLayout
- 13 GitHub stars
- Verilog Synthesis using Yosys for various FPGA targets
- Verilog Simulation using Icarus Verilog with automated testbench execution
- Waveform Viewing and signal analysis with GTKWave
- Complete RTL-to-GDSII ASIC Design Flow via OpenLane with Docker
使用案例
- Automating Verilog synthesis for FPGA or ASIC targets using AI prompts.
- Performing Verilog design simulation with automated testbench generation and waveform viewing via AI.
- Executing complete RTL-to-GDSII ASIC design flows and analyzing PPA metrics with AI assistance.
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