Converts TL-Verilog files into SystemVerilog/Verilog by wrapping Redwood EDA’s SandPiper-SaaS compile function.
This MCP server wraps Redwood EDA’s SandPiper-SaaS compile function, enabling the conversion of TL-Verilog (TLV) files into SystemVerilog/Verilog. It exposes every SandPiper flag as its own MCP tool parameter, allowing for detailed introspection and easy automation of the compilation process. Users can specify compiler behavior using natural language, making it highly accessible.
主要功能
01Uses UV for environment and dependency management
02Exposes Sandpiper flags as MCP tool parameters
030 GitHub stars
04Configurable with Cline/Claude Desktop via JSON
05Can be run with UV or UVX
06Supports TL-Verilog to SystemVerilog/Verilog conversion
使用案例
01Automating TL-Verilog compilation workflows
02Integrating TL-Verilog compilation into MCP-based development environments
03Experimenting with different Sandpiper compiler flags
