Refines ambiguous SystemVerilog requests through interactive clarification and architectural trade-off analysis.
GateFlow Expand serves as an intelligent routing and discovery layer for SystemVerilog development within Claude Code. When a user's request is complex or ambiguous—such as starting a new RTL module without defined interfaces or debugging a non-specific simulation error—this skill intervenes to ask targeted questions and present implementation options with clear pros and cons. By standardizing the requirement-gathering phase, it ensures that subsequent coding tasks are executed with maximum precision and contextual alignment, significantly reducing iteration cycles in hardware design and verification workflows.
主要功能
01Automated building of JSON specifications for downstream coding tasks
02Enriched context handoff to specialized GateFlow agents and tools
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04Interactive multi-choice clarification for hardware interfaces and protocols
05Trade-off analysis presenting multiple implementation architectures to the user
06Intelligent intent disambiguation for RTL design and verification tasks
使用场景
01Diagnosing vague simulation failures such as X-propagation, hangs, or incorrect outputs
02Determining the best interface protocol (AXI-Stream, AXI-Lite, or Ready/Valid) for a new RTL module
03Drafting high-level architectural plans before committing to full SystemVerilog implementation
