Refines ambiguous hardware design requests through interactive clarification and expert architectural options.
Gateflow Expand acts as an intelligent triage and planning layer for SystemVerilog development within the Gateflow ecosystem. It activates when user intent is complex or ambiguous, guiding developers through targeted questions regarding interface protocols, debug symptoms, or architectural depth. By presenting structured implementation options with detailed pros and cons, it ensures that Claude has the precise context needed to generate high-quality RTL code or simulation testbenches, significantly reducing iterative errors and streamlining the handoff to specialized Gateflow agents.
主要功能
01Intelligent intent disambiguation with confidence-based activation
02Quick Start defaults for rapid prototyping and exploration
03Enriched JSON context generation for seamless subagent handoffs
04Architectural trade-off analysis for protocols like AXI-Stream and AXI-Lite
05Context-aware question templates for RTL creation, debugging, and planning
0635 GitHub stars
使用场景
01Selecting the optimal hardware interface protocol based on project constraints
02Diagnosing complex simulation failures through symptom-based triaging
03Narrowing down technical specifications for new SystemVerilog modules
