Is my learning progress saved?

Yes, all your progress, completed exercises, and hints used are tracked locally in a JSON file within your project's .gateflow directory.

Can I get help if I get stuck on a SystemVerilog exercise?

Yes, the skill includes a /gf-learn hint command that provides progressive hints to help you solve the problem without giving away the full solution immediately.

What topics does the gf-learn skill cover?

It covers a wide range of hardware design topics including basic signals, Finite State Machines (FSM), FIFOs, clock domain crossing (CDC), arbiters, memory interfaces, and AXI-Lite protocols.

How does the skill review my code?

When you submit a solution using /gf-learn check, the skill invokes a specialized tutor agent to analyze your RTL code for correctness, timing issues, and best practices.

GateFlow SystemVerilog Learning Mode

Name: GateFlow SystemVerilog Learning Mode
Author: codejunkie99

bycodejunkie99

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学习与文档

Facilitates interactive SystemVerilog mastery through curriculum-based exercises, automated solution reviews, and guided hints.

The gf-learn skill transforms Claude into a specialized RTL tutor, offering a structured path for engineers to master SystemVerilog and hardware design principles. It provides hands-on exercises ranging from basic signals to complex digital logic like FSMs, FIFOs, and AXI-Lite protocols. By generating local starter files and utilizing a dedicated tutor agent for solution review, it provides a feedback loop that helps developers build production-grade RTL skills directly within their terminal. It is ideal for software engineers transitioning to hardware or experienced designers looking to sharpen their skills in specific domains like CDC or pipeline management.

主要功能

01Progressive hint system that guides users without revealing solutions

0228 GitHub stars

03Automated solution validation using a specialized SV-tutor agent

04Support for advanced hardware patterns including backpressure and arbitration

05Curriculum-based exercises covering FSMs, FIFOs, CDC, and bus protocols

06Automatic starter file generation and local progress tracking

使用场景

01Onboarding engineers to RTL design and hardware description languages

02Interview preparation for digital design and verification roles

03Upskilling hardware teams on modern SystemVerilog patterns and best practices

What are Skills?·How to Install

Install with 🐟 Skill.Fish

npx skillfish add codejunkie99/gateflow-plugin gf-learn

For use in Claude.ai and ChatGPT

Download Skill