What happens if a simulation fails during the build process?

Gateflow automatically triggers an orchestration loop, spawning a debug agent to identify the root cause and a refactor agent to fix the code until the verification gates pass.

Does Gateflow support hardware verification?

Yes, Gateflow includes dedicated verification cycles using linting and simulation tools to ensure delivered code is functional, compliant, and ready for implementation.

Can I use Gateflow for existing RTL projects?

Absolutely. Gateflow can debug, refactor, and add testbenches to existing SystemVerilog codebases by spawning specialized agents to analyze and modify your current files.

How does Gateflow handle complex design requirements?

It follows a mandatory planning phase using the sv-planner agent to create ASCII diagrams and protocol summaries before any code is generated, ensuring architectural alignment.

Gateflow SystemVerilog Orchestrator

Name: Gateflow SystemVerilog Orchestrator
Author: codejunkie99

bycodejunkie99

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开发者工具

Orchestrates the end-to-end design, verification, and debugging of production-grade SystemVerilog RTL using natural language.

Gateflow (gf) is a specialized development assistant that transforms high-level requirements into fully verified hardware designs. It acts as the primary entry point for SystemVerilog tasks, enforcing a rigorous 'plan-build-verify' workflow that ensures code is lint-clean and simulation-tested before delivery. By leveraging a multi-agent architecture, Gateflow handles complex RTL creation, parallelized building, and automated debugging loops, providing hardware engineers with a sophisticated, AI-driven environment for delivering working silicon-ready code.

主要功能

01Automated linting and simulation verification gates

02Retrieval-first documentation handling for repository standards

03Parallelized hardware building via specialized sub-agents

04End-to-end RTL orchestration from planning to delivery

05Intelligent debugging and iterative code refactoring

0635 GitHub stars

使用场景

01Automating the identification and fixing of linting errors and simulation mismatches

02Generating complex RTL modules like FIFOs or UARTs with self-checking testbenches

03Drafting detailed implementation plans and block diagrams for new hardware features

What are Skills?·How to Install

Install with 🐟 Skill.Fish

npx skillfish add codejunkie99/gateflow-plugin gf

For use in Claude.ai and ChatGPT

Download Skill