Which hardware languages are supported?

This skill is specifically optimized for SystemVerilog and Verilog development within the Verilator toolchain environment.

Do I need Verilator installed to use this skill?

Yes, this skill requires Verilator to be installed on your system as it invokes the local 'verilator' binary to perform the linting analysis.

Does it provide suggestions on how to fix RTL errors?

Yes, for each issue found (such as width mismatches or unused signals), the skill provides a specific fix suggestion and a prioritized list of recommendations.

What does the GateFlow Summary skill do?

It runs the Verilator lint tool on your SystemVerilog files and generates a clean, readable summary of any errors or warnings found, including fix suggestions.

How do I trigger the summary report?

You can use commands like '/gf-summary' to summarize the last lint output or provide a filename like '/gf-summary sync_fifo.sv' to run a fresh check.

GateFlow Verilator Lint Summary

Name: GateFlow Verilator Lint Summary
Author: codejunkie99

bycodejunkie99

•

安全与测试

Simplifies SystemVerilog development by converting complex Verilator lint and simulation outputs into actionable, readable reports.

GateFlow Summary (gf-summary) is a specialized Claude Code skill designed for hardware engineers working with SystemVerilog and Verilator. It automates the process of running lint checks, parsing verbose compiler output, and presenting a structured summary of errors and warnings. By providing specific line numbers, issue descriptions, and prioritized fix suggestions, it streamlines the RTL debugging process and helps maintain high code quality in digital design projects without requiring the developer to manually sift through terminal logs.

主要功能

01Automated Verilator lint execution with -Wall and --lint-only flags

02Detailed issue breakdown with specific line references

0328 GitHub stars

04Concise status tables showing error and warning counts

05Actionable fix suggestions for common SystemVerilog lint errors

06Prioritized recommendations for hardware debugging workflows

使用场景

01Debugging SystemVerilog RTL during the initial design phase

02Quickly reviewing lint results for large, complex hardware modules

03Ensuring code quality and lint-clean status before logic synthesis

What are Skills?·How to Install

Install with 🐟 Skill.Fish

npx skillfish add codejunkie99/gateflow-plugin gf-summary

For use in Claude.ai and ChatGPT

Download Skill