SystemVerilog Module Scaffolder

关于

The SystemVerilog Module Scaffolder skill automates the creation of high-quality RTL modules by providing a robust template that adheres to the SVC (SystemVerilog Components) architectural standards. It ensures consistency across hardware designs by automatically handling boilerplate tasks such as include guards, standard port declarations (clock and reset), and logic separation. This skill is particularly useful for hardware engineers who need to maintain clean, lint-ready codebases while accelerating the initial design phase of FPGA or ASIC components.

主要功能

• Standardized SystemVerilog template with automated include guards
• Directory structure guidance for AXI, CDC, FIFO, and RISC-V modules
• Pre-configured port ordering for clk, rst_n, and data signals
• Built-in logic blocks for combinational and sequential processes
• 0 GitHub stars
• Integrated quality checklist for formatting and linting compliance

使用场景

• Enforcing consistent coding standards across a team's SystemVerilog repository
• Bootstrapping new RTL modules for FPGA or ASIC hardware projects
• Rapidly setting up specialized modules like FIFOs, UARTs, or Clock Domain Crossings